Textron Systems (Weapon Systems)

Overview

During my time at Textron Systems (Weapon Systems), I worked as an Electrical Engineer supporting the Ground Based Strategic Deterrent (GBSD) Sentinel Program, specifically on the Re-entry System Electronics (RSE). The GBSD Sentinel Program, led by the U.S. Air Force and Northrop Grumman, is a modernization effort replacing the aging Minuteman III ICBM system, ensuring the continued reliability and effectiveness of the nation's strategic deterrent.

Textron Systems' (Weapon Systems) division provides advanced electronic assemblies and mission-critical components for defense applications. Within that effort, my work contributed to the design verification, test, and sustainment of the RSE, a key subsystem responsible for ensuring system reliability under extreme launch and re-entry conditions. I collaborated with cross-functional teams on test planning, schematic validation, and component analysis to help ensure the system met stringent military and environmental standards supporting national defense objectives.

Role & Team

As part of the Terminal Protection Assembly (TPA) and A/DD (Arm/Disarm Device) teams within Textron Systems (Weapon Systems), I supported circuit design, schematic updates, and integration tasks under the guidance of a shared subject matter expert who oversaw both projects. My responsibilities included reviewing and revising PCB schematics, coordinating component selections, and validating signal integrity across interconnected boards. I collaborated closely with the layout, mechanical, and assembly teams to address space claims, connector placements, and wiring routes-ensuring each design met form, fit, and function requirements within strict physical and environmental constraints.

When I first joined the program, I also spent time supporting the FPGA and CCA test teams, helping perform turn-on and turn-off timing tests, troubleshooting board-level functionality, and assisting in lab data collection for test readiness reviews. Over time, my role expanded to include design verification, schematic maintenance, and cross-team coordination during design reviews and build events. I worked in a highly collaborative environment that combined structured milestone reviews with fast-turnaround lab testing to resolve design challenges and maintain production timelines.

Highlights

• Designed, analyzed, and optimized motor control and timing circuits using OrCAD Capture and LTspice simulations, reducing component count by 45% while maintaining operational performance.
• Reworked and consolidated Arc Suppression and switch plate circuitry, integrating protection features directly onto the Terminal Protection Assembly (TPA) and improving maintainability.
• Authored and revised connector and interconnection schematics (P107, switch plate, TPA) to meet electrical and mechanical requirements, ensuring consistency across multi-board assemblies.
• Conducted Design of Experiments (DOE) in MiniTab and performed tin whisker risk analysis using the Pinsky Algorithm to assess and mitigate CCA reliability concerns.
• Supported FPGA testing and validation of circuit card assemblies using oscilloscopes, logic analyzers, and custom Python data-capture scripts.
• Created Visio wiring diagrams and point-to-point connection maps for complex switch stacks (>180 wires), which were adopted by mechanical and assembly teams to streamline harness fabrication.
• Collaborated with firmware, mechanical, and layout teams to perform space claim analyses, enabling cross-disciplinary optimization of electrical design within tight enclosures.
• Introduced standardized naming conventions and component documentation across multiple circuit iterations, improving configuration control and traceability.
• Designed and documented MOSFET-based voltage control circuits for motor protection, including transient suppression and timing cutoff to prevent overheating.
• Modeled and simulated transient behavior and leakage current paths under varying operational conditions to validate safety and reliability of power electronics.
• Shadowed PCB layout specialists using Allegro PCB Editor, gaining exposure to physical layout design and DFM (Design for Manufacturability) practices.

Tech & Tools

Challenges

Integrating protection features without blowing the space claim. The TPA and switch-plate stack had strict mechanical limits. I moved arc-suppression/timing functionality onto the TPA and iterated connector placements with mechanical and layout to keep clearances while preserving electrical performance.

Quantifying reliability risk early. With mixed finish stacks and long service life, I used DOE in Minitab and applied the Pinsky tin-whisker model to frame risk and guide mitigations rather than relying on anecdotal history.

Untangling complex wiring for build/test. Multi-board switch stacks (>180 conductors) were error-prone. I produced point-to-point maps and Visio diagrams that became the single source of truth for assembly and debug.

Outcomes & Impact

• Simplified integration by consolidating protection circuitry on the TPA; reduced part variants and eased troubleshooting.
• Improved build accuracy and test readiness with standardized interconnect docs and wiring maps adopted by mech/assembly.
• Raised confidence in long-term reliability with structured DOE and tin-whisker risk assessments feeding program reviews.
• Better configuration control through naming conventions and schematic documentation across iterations.

Gallery